Search - altera nios

[VHDL-FPGA-Verilog] FPGA_Audio_Player

Description: Altera FPGA SD卡播放音乐程序，基于Nios，强力推荐！-Altera FPGA SD card music program, based on the Nios, highly recommended!
Platform: | Size: 606208 | Author: 任力争 | Hits:

[VHDL-FPGA-Verilog] Qsys_nios2

Description: 本教程使用最新的Quartus 11.0sp1+Nios 11.0sp1开发工具。在最新的Quartus II软件中，使用了全新的Qsys进行SOPC系统的构建。较之以前版本使用SOPC Builder构建有了很大的不同。本教程为Altera最新的官方Tutorial。一步步教你使用Qsys构建Nios II系统，并使用Nios II SBT开发应用程序。-This tutorial uses the latest Quartus 11.0sp1+ Nios 11.0sp1 development tools. In the latest Quartus II software, the use of a new build Qsys the SOPC system. Than the previous version has been using the SOPC Builder to build a big difference. This tutorial Altera' s latest official Tutorial. Step by step to teach you to use Qsys build Nios II system, and use the Nios II SBT application development.
Platform: | Size: 2358272 | Author: | Hits:

[MiddleWare] downstream_pipeline

Description: Altera NIOS II 软核的downstreampipeline-downstreampipeline in NIOS II
Platform: | Size: 1024 | Author: zy | Hits:

[Embeded-SCM Develop] CFI_FLASH

Description: Altera NIOS IICFI 驱动-cfi driver in NIOS II
Platform: | Size: 5120 | Author: zy | Hits:

[VHDL-FPGA-Verilog] vehicle-mounted-display-system

Description: 倒车影像系统FPGA设计，基于ALTERA的NIOS系统的车载显示系统(车载摄像头和TFT显示器)设计源代码，集成仿真环境QUARTUS II7.0及NIOS 7.0,高等级版本可兼容-Reversing video system FPGA design, based on ALTERA NIOS system of vehicle display system (Car Camera and TFT displays) design source code, integrated simulation environment QUARTUS II7.0 and NIOS 7.0, compatible with high-grade version of the
Platform: | Size: 769024 | Author: 杨平平 | Hits:

[VHDL-FPGA-Verilog] Nios-Doom

Description: Altera-DE2 board Doom game player Copy .elf to flash and doom2.wad to an sdcard fat32 to play.
Platform: | Size: 6036480 | Author: Tak | Hits:

[VHDL-FPGA-Verilog] RS232

Description: （6）实验6：串口通讯实验，完整的设计工程文件在RS232文件夹下二、运行环境程序在以下环境调试通过：（1）Windows XP；（2）Altera公司的Quartus II 8.0 for windows；（3）Altera公司的Nios II 8.0 IDE for windows；（4）Mentor公司的ModelSim SE 6.0；-(6) (2) Altera Corporation Quartus II 8.0 for windows Experiment 6: serial communication experiment, a complete design engineering documents RS232 file folder Second, the operating environment program in the following environment debugging through: (1) Windows XP ( Company 3) Altera Nios II 8.0 IDE for windows (4) Mentor ModelSim SE 6.0
Platform: | Size: 14114816 | Author: boyzone | Hits:

[Com Port] PC2NIOSII_uart

Description: Altera Nios II 串口相关程序-Altera Nios II serial program
Platform: | Size: 93184 | Author: annlair | Hits:

[Other Embeded program] wm8731demo.tar

Description: wm8731demo de0 iic altera nios-wm8731demo de0 iic altera niosii
Platform: | Size: 3635200 | Author: 杨琼华 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 使用altera公司的NIOS核完成串口通信开发-Use altera NIOS core company completed the development serial communication
Platform: | Size: 3072 | Author: 马福博 | Hits:

[Industry research] 1211794911-altera-video-surveillance

Description: altra nios II video system
Platform: | Size: 2598912 | Author: rsa2013 | Hits:

[VHDL-FPGA-Verilog] Altera-EP2C8Q-Nios-Example

Description: Altera EP2C8Q Nios例程-Altera EP2C8Q Nios Examples
Platform: | Size: 26194944 | Author: song | Hits:

[Other] IrDA

Description: DE2开发板所付实例，红外无线通信IP核，嵌入式IP核。-altera nios II
Platform: | Size: 450560 | Author: 廖大成 | Hits:

[LabView] VGA

Description: VGA video controller for the Altera Nios II Processor v4.0
Platform: | Size: 310272 | Author: DDD | Hits:

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[VHDL-FPGA-Verilog] FPGA_Audio_Player

[VHDL-FPGA-Verilog] Qsys_nios2

[MiddleWare] downstream_pipeline

[Embeded-SCM Develop] CFI_FLASH

[VHDL-FPGA-Verilog] vehicle-mounted-display-system

[VHDL-FPGA-Verilog] Nios-Doom

[VHDL-FPGA-Verilog] RS232

[Com Port] PC2NIOSII_uart

[Other Embeded program] wm8731demo.tar

[VHDL-FPGA-Verilog] uart

[Industry research] 1211794911-altera-video-surveillance

[VHDL-FPGA-Verilog] Altera-EP2C8Q-Nios-Example

[Other] IrDA

[LabView] VGA

[Embeded-SCM Develop] auto_baud_with_tracking

[Embeded-SCM Develop] bcd_to_binary

[Embeded-SCM Develop] binary_to_bcd

[VHDL-FPGA-Verilog] H891

[Embeded-SCM Develop] memoire_alphabet

[Embeded-SCM Develop] reg_8_io_clrset

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